New Tiled Data Manager ideas and tests

[Dmitry Kazakov]

>
> It's a bug. The next time a user calls
> KisTileReadWriteProcessor::setupProcessor() or
> KisTileReadWriteProcessor::KisTileReadWriteProcessor() with different args
> and then calls copyData, dataIdx won't be set to the correct value.
>

=)
It's done purposely to test this speed boost. More than that with current
test-suite it works fine as applyProcessor calls setupProcessor() with the
same data-pointer all the times. I know it's dirty hack, but, all the same,
i'm going to change processors' interface now.

And good news! I think i found the cause of this speed doubling. It's cache
misses. I managed to run callgrind with special options, and test ran like
on real processor - cache read misses was almost 90% on the version before
commit :)

PS:
valgrind --tool=callgrind  --I1=65536,1024,16 --D1=65536,1024,16
--L2=262144,1024,32 ./dm_perfomance_test

PS: I'm not sure about associativity, but my caches are L1: 64+64KiB, L2:
256KiB


-- 
Dmitry Kazakov
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