Floating idea Schematic to Verilog for SOC's with analog and/or FPGA alongside.

[Zoltan Padrah]

>   Is there any support for developing KtechLab schematic to Verilog
outputs for PSoC family (or even embedded FPGA)  so that we can do visual
design (for small projects)?

If I understand correctly, you would like to make digital schematics in
KTechLab and then converting that schematic to Verilog, in order to be used
with other tools ?

I think such functionality would be useful and very nice.

Currently this is not implemented, but should be doable in a relatively
easy manner. Just adding an Export to Verilog function to Circuit
documents. In there go though the components, output some Verilog code for
each component and connect the modules with some more Verilog code.
If someone implements this, I would review it and merge it.

Slightly off-topic:
I have been thinking about Verilog Code components for KTechLab: have a
component in KTechLab in which Verilog code can be edited, and it has a
button "Synthesise", clicking that will make the text read-only and the
pins of the Verilog module appear outside of the component, and it behaves
just as the Verilog code describes. It would be useful for fast logic
prototyping. Only if I had time for have fun with such pet-projects...


Best regards,

 Zoltan



WADE MAXFIELD <wade.maxfield at 4gwireline.com> ezt írta (időpont: 2021. jan.
15., P, 22:19):

>  Resend:  sent from wrong email.
>
> Hi,
>
>   I develop using SOC devices.  My current favorite is the PSoC 5 from
> Cypress.  They were recently acquired by Infineon.
>
>   They appear to be changing their approach from visual schematic design
> to only code.  I prefer visual when possible.
>
>   They have created Modus Toolbox (MT) which has totally done away with
> the visual schematic designer.  It also does not support PSOC family prior
> to their PSOC 6 SOC versions.
>
>   However, MT tools will more or less support the PSOC 5 family. Even if
> there are problems with certain tools, we can run the Windows command line
> tools under Wine, including the GCC compiler.  I have done this.
>
>   Wine does not properly support the graphics requirements of the PSoC
> Creator program.  Many crashes occur.
>
>
>   Personally, I have written VHDL and Verilog for logic, along with coding
> in about a dozen other languages for processor execution, but I still think
> visually.
>
>
>   The PSOC family,  has some digital fabric inside of it along with a lot
> of analog components, all routable through Verilog.
>
>   The amount of logic and analog that can be placed into a PSOC 5 design
> is impressive, based on my experiences.
>
>   In addition, there are a lot of FPGA’s out there that have embedded
> CPU’s, and more small FPGA’s are being created with embedded CPU’s as time
> passes.
>
>
>   This all appears to be a unique fit for the ktechlab concept as I
> understand it.
>
>
>   Is there any support for developing KtechLab schematic to Verilog
> outputs for PSoC family (or even embedded FPGA)  so that we can do visual
> design (for small projects)?
>
>  I have thick skin, so feel free to flame away.  Everyone has an opinion,
> and everyone’s opinion is correct, when taken in the context in which it is
> given.
>
>
> thanks!
> Wade
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>
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