[Uml-devel] Brief intro

[Fred Roberts]

Hello, I am Fred.  I am an Electrical Engineer.  I started my career out 
designing
chips using Verilog, and VHDL.   After a couple of years of that I moved 
over to
chip design verification.  There are languages devoted to that very task 
Open Vera
http://www.open-vera.com is what I use primarily at the moment.  These 
verification
languages are object oriented in nature, but most verification engineers 
don't follow
OO practices while designing test environments, and components.  They 
use their
own personal methods, if any, to document the design making maintenance 
a nightmare
if you have to pick up someone else's work.  I ramble . . .

I would like to contribute to umbrello, mainly in the plugin area.  I 
would be willing
to help document the plugin interface, and would like to write a plugin 
for OpenVera.  
I looked at several tools, and none supported hardware verification 
languages, and none
had a plugin interface so fitting them to support new languages isn't as 
practical.  

I know that you are currently trying to get 1.1 out the door, and that 
what I am interested in
would come later, but I just thought I would say hello.

Regards,
Fred