Wireshark + qt5-core with CPU Alderlake and AVX512

Francois Ranchin fyr at free.fr
Wed Jun 21 05:17:27 BST 2023 

Dear maintainers,


I have a new Intel NUC 12th generation https://ark.intel.com/content/www/us/en/ark/products/121613/intel-nuc-12-pro-kit-nuc12wski3.html
under freebsd release 13.2

Running wireshark from ports or from source end with :

[1]    3187 illegal hardware instruction (core dumped)  wireshark

After some research and try I think it’s a AVX-512 related trouble.

1 - lldb inside the core just show the same pattern with qt5-core ans SIGILL


2 - Intel physically fused off AVX-512 after non uniformity trouble between Efficiency and Performance core. https://en.wikipedia.org/wiki/Alder_Lake P core and E cores have different set of instructions.

“AVX-512 (including FP16) is present but disabled by default to match E-cores. On early revisions of microprocessors it still can be enabled on some motherboards with some BIOS versions by disabling the E-cores.[18][19] Intel has physically fused off AVX-512 on later revisions of Alder Lake CPUs manufactured in early 2022 and onward.[20][21]”

qt5-core can’t obey to instruction to remove AVX-512. Quick force removing AVX512 in the source leads to this error :

Incompatible processor. This Qt build requires the following features:
   X5^!!
Aborted. Incompatible processor: missing feature 0xc2000000 -X.
[1]    13603 abort (core dumped)  wireshark



——————————————————
make config of at5-core :
Checking for AVX512 F instructions... yes
Checking for AVX512 BW instructions... yes
Checking for AVX512 CD instructions... yes
Checking for AVX512 DQ instructions... yes
Checking for AVX512 ER instructions... yes
Checking for AVX512 IFMA instructions... yes
Checking for AVX512 PF instructions... yes
Checking for AVX512 VBMI instructions... yes
Checking for AVX512 VL instructions... yes
[…]
Checking for AVX512 F instructions... yes
Checking for AVX512 BW instructions... yes
Checking for AVX512 CD instructions... yes
Checking for AVX512 DQ instructions... yes
Checking for AVX512 ER instructions... yes
Checking for AVX512 IFMA instructions... yes
Checking for AVX512 PF instructions... yes
Checking for AVX512 VBMI instructions... yes
Checking for AVX512 VL instructions... yes
——————————————————

BUT

————————————————————
llvm-tblgen -version
LLVM (http://llvm.org/):
  LLVM version 11.0.1
  Optimized build.
  Default target: x86_64-unknown-freebsd13.0
  Host CPU: goldmont
—————————————————————

goldmont is an old Atom CPU rebranded inside the E-core of the new non uniform Intel CPU… The E-core is likely to be this old Atom architecture.


—————————————————————
cc -v -x c -E -march=native /dev/null -o /dev/null

FreeBSD clang version 14.0.5 (https://github.com/llvm/llvm-project.git llvmorg-14.0.5-0-gc12386ae247c)
Target: x86_64-unknown-freebsd13.2
Thread model: posix
InstalledDir: /usr/bin
 (in-process)
 "/usr/bin/cc" -cc1 -triple x86_64-unknown-freebsd13.2 -E -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name null -mrelocation-model static -mframe-pointer=all -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu alderlake -target-feature -avx512pf -target-feature -tsxldtrk -target-feature +cx16 -target-feature +sahf -target-feature -tbm -target-feature -avx512ifma -target-feature +sha -target-feature +crc32 -target-feature -fma4 -target-feature +vpclmulqdq -target-feature +prfchw -target-feature +bmi2 -target-feature -cldemote -target-feature +fsgsbase -target-feature +ptwrite -target-feature -amx-tile -target-feature -uintr -target-feature +gfni -target-feature +popcnt -target-feature -widekl -target-feature +aes -target-feature -avx512bitalg -target-feature +movdiri -target-feature +xsaves -target-feature -avx512er -target-feature +avxvnni -target-feature -avx512fp16 -target-feature -avx512vnni -target-feature -amx-bf16 -target-feature -avx512vpopcntdq -target-feature -pconfig -target-feature +clwb -target-feature -avx512f -target-feature +xsavec -target-feature -clzero -target-feature +pku -target-feature +mmx -target-feature -lwp -target-feature +rdpid -target-feature -xop -target-feature +rdseed -target-feature +waitpkg -target-feature -kl -target-feature +movdir64b -target-feature -sse4a -target-feature -avx512bw -target-feature +clflushopt -target-feature +xsave -target-feature -avx512vbmi2 -target-feature +64bit -target-feature -avx512vl -target-feature +serialize -target-feature +hreset -target-feature +invpcid -target-feature -avx512cd -target-feature +avx -target-feature +vaes -target-feature -avx512bf16 -target-feature +cx8 -target-feature +fma -target-feature -rtm -target-feature +bmi -target-feature -enqcmd -target-feature +rdrnd -target-feature -mwaitx -target-feature +sse4.1 -target-feature +sse4.2 -target-feature +avx2 -target-feature +fxsr -target-feature -wbnoinvd -target-feature +sse -target-feature +lzcnt -target-feature +pclmul -target-feature -prefetchwt1 -target-feature +f16c -target-feature +ssse3 -target-feature -sgx -target-feature +shstk -target-feature +cmov -target-feature -avx512vbmi -target-feature -amx-int8 -target-feature +movbe -target-feature -avx512vp2intersect -target-feature +xsaveopt -target-feature -avx512dq -target-feature +sse2 -target-feature +adx -target-feature +sse3 -debugger-tuning=gdb -v -fcoverage-compilation-dir=/home/fyr -resource-dir /usr/lib/clang/14.0.5 -fdebug-compilation-dir=/home/fyr -ferror-limit 19 -fgnuc-version=4.2.1 -fcolor-diagnostics -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /dev/null -x c /dev/null
clang -cc1 version 14.0.5 based upon LLVM 14.0.5 default target x86_64-unknown-freebsd13.2
#include "..." search starts here:
#include <...> search starts here:
 /usr/lib/clang/14.0.5/include
 /usr/include
End of search list.
——————————————————————

=> all AVX512 feature are out from compiler.


confirmed with :

——————————————————————
echo "int foo() { return 0;}" | clang -x c++ - -o - -S -emit-llvm -O2 -march=native


; ModuleID = '-'
source_filename = "-"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-freebsd13.2"

; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone uwtable willreturn
define dso_local noundef i32 @_Z3foov() local_unnamed_addr #0 {
  ret i32 0
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind readnone uwtable willreturn "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="alderlake" "target-features"="+64bit,+adx,+aes,+avx,+avx2,+avxvnni,+bmi,+bmi2,+clflushopt,+clwb,+cmov,+crc32,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+gfni,+hreset,+invpcid,+lzcnt,+mmx,+movbe,+movdir64b,+movdiri,+pclmul,+pku,+popcnt,+prfchw,+ptwrite,+rdpid,+rdrnd,+rdseed,+sahf,+serialize,+sha,+shstk,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+vaes,+vpclmulqdq,+waitpkg,+x87,+xsave,+xsavec,+xsaveopt,+xsaves,-amx-bf16,-amx-int8,-amx-tile,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-cldemote,-clzero,-enqcmd,-fma4,-kl,-lwp,-mwaitx,-pconfig,-prefetchwt1,-rtm,-sgx,-sse4a,-tbm,-tsxldtrk,-uintr,-wbnoinvd,-widekl,-xop" }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 7, !"uwtable", i32 1}
!2 = !{i32 7, !"frame-pointer", i32 2}
!3 = !{!"FreeBSD clang version 14.0.5 (https://github.com/llvm/llvm-project.git llvmorg-14.0.5-0-gc12386ae247c)"}
—————————————————————


—————————————————————
dmesg outpout

CPU: 12th Gen Intel(R) Core(TM) i3-1220P (998.40-MHz K8-class CPU)
  Origin="GenuineIntel"  Id=0x906a4  Family=0x6  Model=0x9a  Stepping=4
  Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE>
  Features2=0x7ffafbbf<SSE3,PCLMULQDQ,DTES64,MON,DS_CPL,VMX,EST,TM2,SSSE3,SDBG,FMA,CX16,xTPR,PDCM,PCID,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,TSCDLT,AESNI,XSAVE,OSXSAVE,AVX,F16C,RDRAND>
  AMD Features=0x2c100800<SYSCALL,NX,Page1GB,RDTSCP,LM>
  AMD Features2=0x121<LAHF,ABM,Prefetch>
  Structured Extended Features=0x239c27eb<FSGSBASE,TSCADJ,BMI1,AVX2,FDPEXC,SMEP,BMI2,ERMS,INVPCID,NFPUSG,RDSEED,ADX,SMAP,CLFLUSHOPT,CLWB,PROCTRACE,SHA>
  Structured Extended Features2=0x984007bc<UMIP,PKU,OSPKE,WAITPKG,GFNI,VAES,VPCLMULQDQ,RDPID,MOVDIRI,MOVDIR64B>
  Structured Extended Features3=0xfc18c410<FSRM,MD_CLEAR,IBT,IBPB,STIBP,L1DFL,ARCH_CAP,CORE_CAP,SSBD>
  XSAVE Features=0xf<XSAVEOPT,XSAVEC,XINUSE,XSAVES>
  IA32_ARCH_CAPS=0x88fd6b<RDCL_NO,IBRS_ALL,SKIP_L1DFL_VME,MDS_NO,TAA_NO>
  VT-x: PAT,HLT,MTF,PAUSE,EPT,UG,VPID,VID,PostIntr
  TSC: P-state invariant, performance statistics
—————————————————————


So qt5-core includes AVX512 instructions while they are not present in the CPU (confirmed by wiki, external sources, compiler results and dmesg outpout)



Do you have a solution ? (i tried forced removed of avx512 in source without succes I suspect others ports with the same problems) Of course it’s OK with my older 5th generation CPU without AVX512 at all.


Kind regards,

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